knowledge_base:professional:dram

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knowledge_base:professional:dram [2023/02/13 21:42] – Normal Userknowledge_base:professional:dram [2023/02/13 23:18] (current) – [DRAM Basics] Normal User
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 ====== DRAM Basics ====== ====== DRAM Basics ======
  
-[[https://www.systemverilog.io/ddr4-basics|DRAM Basics]]+[[https://www.systemverilog.io/ddr4-basics|DDR4 SDRAM - Understanding the Basics]]
  
-===== High Level =====+[[https://www.systemverilog.io/ddr4-initialization-and-calibration|DDR4 SDRAM - Initialization, Training and Calibration]]
  
-{{:knowledge_base:professional:dram:pasted_20230213_213637.png}}+[[https://www.youtube.com/watch?v=dacVFxuaivQ|Signals on DDR4 DRAM]] 
 + 
 +[[https://www.youtube.com/watch?v=t-JocbNXw0k|DDR4 Board Validation Simulation]] 
 + 
 +===== Top Level ===== 
 + 
 +{{:knowledge_base:professional:dram:pasted_20230213_213637.png}} \\ 
 +Figure 1: Top Level
  
 ^Symbol ^Type ^Function^ ^Symbol ^Type ^Function^
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 |BG0-1, BA0-1 |Input |Bank Group, Bank Address| |BG0-1, BA0-1 |Input |Bank Group, Bank Address|
 |A0-13 |Input |Address inputs| |A0-13 |Input |Address inputs|
 +
 +===== BankGroup, Bank, Row, Column =====
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_214246.png?1000}} \\
 +Figure 2: BankGroup & Bank
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_214420.png}} \\
 +Figure 3: Row & Column Decoding
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_214449.png}} \\
 +Figure 4: Bit Level
 +
 +===== DRAM Sizing & Addressing =====
 +
 +DRAMs come in standard sizes and this is specified in the JEDEC spec. JEDEC is the standards committee that decides the design and roadmap of DDR memories. This is from section 2.7 of the DDR4 JEDEC specification (JESD79-4B).
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_215446.png?1000}} \\
 +Figure 5: Addressing
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_215555.png}}
 +
 +==== DRAM Page Size ====
 +
 +In the table above, there's a mention of Page Size. Page size is essentially the number of bits per row. Or put it another way, it is the number of bits loaded into the Sense Amps when a row is activated. Since the column address is 10 bits wide, there are 1K bit-lines per row. So, for a x4 device number of bits is 1K x 4 = 4K bits (or 512B). Similarly, for x8 device it is 1KB and for x16 it is 2KB per page.
 +
 +==== Rank (Depth Cascading) ====
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_215822.png}} \\
 +Figure 6: Rank
 +
 +==== Width Cascading ====
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_215856.png}} \\
 +Figure 7: DRAMs Width Cascading
 +
 +===== Accessing Memory =====
 +
 +==== Command Truth Table ====
 +
 +I'm constantly referring to something called "commands" - ACTIVATE command, PRECHARGE command, READ command, WRITE command. But in the very first picture of this article, there is no "Command" input to the DRAM. So how are these commands issued?
 +
 +Well, the DRAM interprets the ACT_n, RAS_n, CAS_n & WE_n inputs as commands based on the truth table below.
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_220013.png}}
 +
 +The table above is only a subset of commands you can issue to the DRAM. The entire DDR4 command truth table is specified in section 4.1 of the JEDEC spec JESD79-4B.
 +
 +==== Read ====
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_220046.png}} \\
 +Figure 8: READ Operation
 +
 +==== Write ====
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_220115.png}} \\
 +Figure 9: WRITE Operation
 +
 +===== DRAM sub-system =====
 +
 +Now that we've had a sufficiently long discussion about the DRAM, it is time to talk about what the ASIC or FPGA needs in-order to talk to the DRAM. This is called the DRAM sub-system and it's made up of 3 components:
 +
 +  - The DRAM memory itself, which comprises of everything described above
 +  - A DDR PHY
 +  - A DDR Controller
 +
 +{{:knowledge_base:professional:dram:pasted_20230213_220220.png}} \\
 +Figure 10: DRAM Sub-System
 +
 +====== In a Nutshell ======
 +
 +Let's wrap this up
 +
 +The DRAM is organized as Bank Groups, Bank, Row & Columns
 +The address issued by the user is called Logical Address and it is converted to a Physical Address by the DRAM controller, before it presented to the memory
 +DDR4 DRAMs are classified as x4, x8 or x16 based on the width of the DQ data bus
 +You can depth cascade or width cascade DRAMs to achieve the required size
 +Read and write operations are a 2-step process. 1st step activates a row, 2nd step reads or write to the memory.
 +The DRAM sub system comprises of the memory, a PHY layer and a controller
 +
 +
 +
 +
 +
  • Last modified: 2023/02/13 21:42
  • by Normal User