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| knowledge_base:professional:dram [2023/02/13 22:15] – [DRAM Basics] Normal User | knowledge_base:professional:dram [2025/07/28 19:37] (current) – [DRAM Basics DDR DDR4 DDR4X LPDDR LPDDR4X] Normal User |
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| ====== DRAM Basics ====== | ====== DRAM Basics DDR DDR4 DDR4X LPDDR LPDDR4X ====== |
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| [[https://www.systemverilog.io/ddr4-basics|DRAM Basics]] | [[https://www.systemverilog.io/ddr4-basics|DDR4 SDRAM - Understanding the Basics]] |
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| | [[https://www.systemverilog.io/ddr4-initialization-and-calibration|DDR4 SDRAM - Initialization, Training and Calibration]] |
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| [[https://www.youtube.com/watch?v=dacVFxuaivQ|Signals on DDR4 DRAM]] | [[https://www.youtube.com/watch?v=dacVFxuaivQ|Signals on DDR4 DRAM]] |
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| | [[https://www.youtube.com/watch?v=t-JocbNXw0k|DDR4 Board Validation Simulation]] |
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| | [[https://www.jedec.org/sites/default/files/files/Marc_Greenberg_Mobile_and_IOT.pdf|LPDDR4 2-die 4-die architecture]] |
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| | [[https://isolo.org/dokuwiki/private/workplace/ddr_memory|DDR4 SDRAM - Initialization, Training and Calibration]] |
| ===== Top Level ===== | ===== Top Level ===== |
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