# How to calculate the MIPI DSI data rate and how to configure the clock clk

## [DESCRIPTION]

How to calculate the DSI data rate and how to configure the clock clk

## [KEYWORD]

dsidata rate, mipi clk

## [SOLUTION]

**NOTE:** This does not consider the VESA DSC compression ratio. DSC may achieve 1:3 compression ratio.

### 1. The approximate calculation formula of data rate data_rate in DSI vdo mode is:

Data rate= (Height+VSA+VBP+VFP)*(Width+HSA+HBP+HFP)* total_bit_per_pixel*frame_per_second/total_lane_num

### 2. The approximate calculation formula of the data rate data_rate in DSI cmd mode is:

Data rate= width*height*1.2* total_bit_per_pixel*frame_per_second/total_lane_num

**Parameter notes:**

data_rate: indicates the data rate

width, height: screen resolution

VSA VBP VFP: DSI vdo mode vertical porch configuration parameter

HSA HBP HFP: DSI vdo mode horizontal porch configuration parameter

total_bit_per_pixel: indicates that a pixel needs to be used A few bits to represent, such as

RGB565 is 16 bit frame_per_second: is the fps we usually see, called the frame rate, which indicates how many frames are sent per second, generally 60 frames per second

total_lane_num: indicates the data lane number.

### 3. DSI uses bilateral sampling, then clk is equal to half of the data rate, so: clk = data_rate/2

There are two ways to configure clk, the first way is to configure four parameters, and the second way is to directly configure the frequency , The second one is recommended.

The first method is implemented by div frequency division and frequency multiplication. Each platform is slightly different, but the principle is basically the same. Please refer to the porting guide. The following example 89 platforms:

params-> dsi.pll_div1 =;//When the configuration range is 0,1,2,3, the corresponding div1_real is equal to 1, 2, 4, 4

params-> dsi.pll_div2 =;//When the configuration range is 0,1,2,3, the corresponding div2_real is equal to 1, 2, 4, 4

params-> dsi.fbk_div =;//range 0..63

params-> dsi.fbk_sel =;//When the configuration range is 0,1,2,3, the corresponding fbk_sel_real is equal to 1, 2, 4, 4

Output frequency = 26MHz * (fbk_div + 1) * (2 * fbk_sel_real)/(div1_real * div2_real)

The second way is to directly configure the clk size:

params→ dsi.PLL_CLOCK = LCM_DSI_6589_PLL_CLOCK_234;

Here is an example of 89 platforms, using a macro, indicating that the configured clk is equal to 234MHz. But for platforms after 89, use the method of directly configuring a frequency number, such as params→ dsi.PLL_CLOCK = 234, which means 234MHZ)

### 4. In the lcm porting process, these parameters are defined in the LCM_DSI_PARAMS structure in the lcm_drv.h file.

As the platform develops, it may be different, but the basic principles are the same. How to configure the size of clk First calculate the data_rate according to your frame rate, pixel format, porch value, screen resolution, data lane logarithm, etc., and then calculate clk.

Ask later, what does dsi ddr clk rate appear in the datasheet mean does ddr mean double data-rate? Know the answer.